1. Field of the Invention
The present invention relates to the structure of a compound semiconductor field effect transistor, particularly such a transistor having a high breakdown voltage.
2. Description of the Related Art
In power compound semiconductor FET""s (FET stands for field effect transistor) having a high breakdown voltage, a portion of the channel region not covered by the gate electrode, i.e. a non-gate region is formed between the gate electrode and the drain electrode for higher breakdown voltage of drain. Thereby, when a voltage is applied to the drain electrode, depletion occurs in the non-gate region, electric field concentration is prevented, and direct short-circuiting between gate electrode and drain electrode is prevented.
It was found, however, that when a high voltage is applied and an electric current flows through the channel region, there appears a phenomenon that avalanche breakdown takes place and generates holes and the holes flow toward the vicinity of the gate electrode according to the electric field generated, allowing the surface to be positively charged and making the channel more conductive. The mechanism of the phenomenon is shown in FIG. 3. In FIG. 3, 12 is a semi-insulating substrate; 1 is a source electrode; 2 is a gate electrode; 3 is a channel; 4 is a drain electrode; 8 is an electron flow of channel current (a channel electron flow); 9 is an electron flow generated by avalanche breakdown (an avalanche electron flow); 10 is a hole flow generated by avalanche breakdown (an avalanche hole flow); 11 is a surface state of non-gate region; and 26 is a depletion region.
In order to increase the breakdown voltage between drain electrode and gate electrode, it is necessary that the holes generated by avalanche breakdown are allowed not to reach the channel surface of transistor, particularly the vicinity of the gate electrode or that the generation per se of holes is suppressed.
The present invention lies in a compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current (channel direction) and contact with the gate electrode.
The present invention lies in A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current (channel direction) and contact with the gate electrode.
In the compound semiconductor field effect transistor of the present invention, the breakdown voltage between drain and gate can be increased without substantially inviting an increase in parasitic capacity and a decrease in speed.
Further, the compound semiconductor field effect transistor of the present invention, when having no p type layer, can be produced easily because preparation of a new mask is an only step to be added and no use of any new complicated step is needed.